1. Field of the Invention
The present invention generally relates to wiring in integrated circuits (ICs) and, more particularly, to wire shapes which minimize capacitive coupling while maintaining current carrying capacity.
2. Background Description
In a typical integrated circuit device, conductive wires are used to provide electrical contact among devices and chips, and between chips and the outside world. These wires can be fabricated from metal, metal compounds such as silicides or nitrides, or polysilicon depending on the application. For cost and performance reasons, the trend has been to include more conductors of reduced dimensions on a given chip. This is achieved within a wiring plane by reducing the width of the conductors and of the intervening dielectric isolation regions. Additionally, multiple wiring levels can be fabricated sequentially and interconnected in a discretionary manner using short range vertical interconnects (studs).
It is generally desirable for conductors to not limit the speed of the transmitted signals and to not degrade signals in adjacent conductors due to capacitive coupling. However, signal speed is reduced in wires and signals are degraded in neighboring conductors because of capacitive coupling. The reduction in signal speed is in proportion to the wire resistance and capacitance (i.e., RC time constant). The wire resistance is determined by the intrinsic resistivity of wire material and by the wire dimensions, which can be varied within limits set by design and process limitations. Thus, wire resistance is a relatively fixed value for a given design and technology.
Unfortunately, as wires are positioned in close proximity to each other, the wire coupling capacitance increases. The extended field surrounding a current carrying wire intersects neighboring wires, thereby producing an undesirable current in the neighboring wire and weakening the original signal. This effect is known as capacitive coupling or crosstalk, and can be referred to as interlevel or intralevel, depending on whether the wires are located on the same wiring plane.
Accordingly, methods to increase device speed through reduced capacitive coupling have been developed and implemented. In one technique, the dielectric film used to isolate the wires (interlayer dielectric or ILD) can be replaced by a film having a lower dielectric constant. The standard SiO.sub.2 dielectric film has a dielectric constant of about 3.9. Paraszczak et al., Proc. Int'l Electron Device Meeting 1993, pp.261-264 for instance, have shown that a fluoropolymer ILD can yield an effective dielectric constant of 2.6, resulting in a large increase in system performance. In another approach, reduced crosstalk can be obtained by optimizing the cross-sectional dimensions of wires having rectangular cross sections. For example, Sakurai et al., IEEE Trans. Electron Dev. Vol. 40, No. 1, January 1993, have generated expressions for the interlevel coupling capacitance and crosstalk voltage, which were then used to identify the optimum linewidth corresponding to minimum RC delay for a given pitch and conductance.
Despite these efforts, crosstalk between conductors remains a principle limiter of IC speed and is expected to become increasingly severe for future products fabricated at sub half-micron minimum dimensions.